Title :
Primitive path delay fault identification
Author :
Sivaraman, Mukund ; Strojwas, Andrzej J.
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
We present a novel and efficient method to identify all primitive single and multi path delay faults (PDFs) in multi-level combinational circuits. Our method is the first one to successfully target the primitive PDF identification problem for multi-level circuits-previous research results in this area have been limited either to the identification of primitive PDFs only for 2-level circuits, or to the identification of only a subset of the complete set of paths which need not be tested for delay faults. Our primitive PDF identification procedure is based on determining which paths or sets of paths determine the signal stabilization time at the circuit outputs. We demonstrate the feasibility of the approach for mid-sized benchmark circuits
Keywords :
combinational circuits; delays; fault diagnosis; logic testing; multivalued logic circuits; multi path delay fault; multilevel combinational circuit; primitive path delay fault identification; signal stabilization time; single path delay fault; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Fault diagnosis; Propagation delay; Sampling methods; Semiconductor device testing; Timing;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.567968
