A silicon vertex detector with pipelining front-end electronics for H1 at HERA

Summary form only. A silicon vertex detector for tagging secondary vertices from charm decays has been proposed for the H1 experiment. It uses two layers of double-sided silicon strip detectors in a barrel geometry. A beam pipe radius of 35 mm with a horizontal offset of 10 mm from the beam axis is possible at HERA with an upgrade of existing synchrotron radiation masks. Prototypes of the front-end electronics in 2-μm CMOS technology have been successfully tested. The preamplifier has a risetime of 100 ns and an equivalent noise charge of 1400 electrons at 24 pF load while operating with 0.28 mW power per channel. The analog signals are stored in a capacitor pipeline of 32 cells per channel to allow for the level trigger decision time. One channel with preamplifier and pipeline has a width of 44 μm on the chip. The CMOS process is not radiation-hardened but the prototype circuits were functional up to doses of 150 krad, albeit with increased power and noise