Internal ECL-BiCMOS translator circuits in half micron technology

Author

Boudon, Gerard ; Wallart, Frank ; Maillart, Eric

Author_Institution

IBM France, Corbeil-Essonnes, France

fYear

1989

fDate

2-4 Oct 1989

Firstpage

314

Lastpage

317

Abstract

BiCMOS associates high-speed circuits with the low power requirements of CMOS. Traditional BiCMOS circuits are mainly CMOS-based with bipolar buffers to improve driving capability and speed. Increased performance can be obtained with BiCMOS technology if CMOS/BiCMOS circuits are merged with an ECL (emitter-coupled logic) low swing circuit. Mixing of logic is possible if very-high-speed level translators for levels conversion are designed. The benefits of such an approach in 0.5-μm BiCMOS technology have been estimated for the proposed ECL-to-CMOS-level convertor circuits

Keywords

BIMOS integrated circuits; buffer circuits; digital integrated circuits; emitter-coupled logic; integrated circuit technology; 0.5 micron; BiCMOS technology; CMOS-based; CMOS/BiCMOS circuits; ECL; ECL-BiCMOS translator circuits; ECL-to-CMOS-level convertor circuits; bipolar buffers; emitter-coupled logic; half micron technology; high-speed circuits; levels conversion; logic mixing; low power; very-high-speed level translators; BiCMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Converters; Delay; Logic arrays; Registers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-1971-6

Type

conf

DOI

10.1109/ICCD.1989.63379

Filename

63379