DocumentCode :
1927666
Title :
Characterisation of the Overlap Capacitance of Submicron LDD MOSFETs
Author :
Dyaev, V. Kol ; Clerix, A. ; Arteaga, R.Murphy ; Deferm, L.
Author_Institution :
Institute of Semiconductor Physics, Lavrent´´eva av. 13, Novosibirsk-90, 630090, Russia
fYear :
1995
fDate :
25-27 Sept. 1995
Firstpage :
757
Lastpage :
760
Abstract :
The dependence of the gate capacitance Cgds on biasing voltages in currentless regime is discussed for nMOS and pMOS devices. The components of the overlap capacitance are extracted as well as the effective poly and channel length. The influence of processing conditions on the overlap capacitance is shown.
Keywords :
CMOS process; Capacitance measurement; Frequency; Geometry; MOS devices; MOSFET circuits; Physics; Semiconductor device modeling; Substrates; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
Conference_Location :
The Hague, The Netherlands
Print_ISBN :
286332182X
Type :
conf
Filename :
5436120
Link To Document :
بازگشت