• DocumentCode
    1927738
  • Title

    A high speed array architecture for 2-D wavelet transform

  • Author

    Limqueco, Jimmy C. ; Bayoumi, Magdy A.

  • Author_Institution
    Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
  • Volume
    3
  • fYear
    1996
  • fDate
    18-21 Aug 1996
  • Firstpage
    1239
  • Abstract
    In this paper, an efficient, simple and fast systolic-like architecture for a 2-D Discrete Wavelet Transform (DWT) is proposed. The “approximation” and “detailed” components of a signal are computed simultaneously in the first octave and alternately in other octaves. Each processing element has its own local memory for storing the intermediate data. The proposed architecture uses the same clock frequency for every octave level. It has a 100% utilization for a 2-octave level architecture, and N2+N period cycle. The architecture is scalable for different filter length (divisible by 2) and different octave levels
  • Keywords
    VLSI; digital filters; digital signal processing chips; systolic arrays; transforms; wavelet transforms; 2-octave level architecture; 2D DWT; 2D wavelet transform; DSP chip; clock frequency; discrete wavelet transform; high speed array architecture; systolic-like architecture; Clocks; Computer architecture; Delay; Discrete wavelet transforms; Electronic mail; Filters; Upper bound; Very large scale integration; Wavelet transforms; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996., IEEE 39th Midwest symposium on
  • Conference_Location
    Ames, IA
  • Print_ISBN
    0-7803-3636-4
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1996.593135
  • Filename
    593135