• DocumentCode
    1927756
  • Title

    A Triple-well Architecture for Low-voltage Operation in Submicron CMOS Devices

  • Author

    Auricchio, C. ; Bez, R. ; Losavio, A. ; Maurelli, A. ; Sala, C. ; Zabberoni, P.

  • Author_Institution
    SGS-Thomson Microelectronics, Central R&D, Via C. Olivetti 2 - 20041 Agrate Brianza - ITALY
  • fYear
    1996
  • fDate
    9-11 Sept. 1996
  • Firstpage
    613
  • Lastpage
    616
  • Abstract
    In this work, we present an investigation of a triple-well process architecture for sub-half- micron CMOS technologies. The characterization presented here includes simulation of the manufacturing process as well as an evaluation of the electrical performance of the triple-well structures, active devices and parasitic elements.
  • Keywords
    Bipolar transistors; CMOS process; CMOS technology; Diodes; Implants; Low voltage; Manufacturing processes; Microelectronics; Research and development; Thyristors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
  • Conference_Location
    Bologna, Italy
  • Print_ISBN
    286332196X
  • Type

    conf

  • Filename
    5436124
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1927756