First level muon trigger circuits using Xilinx FPGA

Drift tubes of the SDC central muon detector in θ view are used to generate a first level muon trigger. The authors first describe the basic trigger concept developed by the SDC muon subgroup. Results from a Monte Carlo study are given. A design for implementing the basic trigger concept using the Xilinx FPGA (field-programmable gate array) is discussed. The complete flexibility of the FPGA makes it possible to program the trigger logic after the experiment is turned on, making it possible to overcome unexpected problems. This is very valuable for an expensive trigger system which will be operated for more than 10 years under varying experimental conditions