First level calorimeter trigger system for the Large Hadron Collider

As part of an R&D project to study first-level calorimeter triggers for the Large Hadron Collider (LHC), an application specific integrated circuit (ASIC) has been designed which will search for candidate electromagnetic (EM) clusters associated with a particular cell from a 4×4 area of the calorimeter. The ASIC takes in 16 (4×4) 8-bit digitized signals from the calorimeter and will provide two results: (1) a flag to indicate the presence of an EM cluster and (2) a sum over the 4×4 area which will be used in the subsequent logic in the trigger system to search for jets and to calculate missing transverse energy. In the LHC the bunch-crossing period is 15 ns, and therefore the logic is implemented on the ASIC using a pipelined architecture, which pipeline steps of 15 ns. The algorithm has been implemented on a 0.8-μ CMOS gate array, and is packaged in a 179-pin ceramic pin grid array. The ASIC has been tested above the full operating frequency of 67 MHz