A new amplifier and pipeline chip for silicon strip detector readout

Summary form only. A silicon vertex detector has been proposed for the H1 experiment at HERA. The bunch crossing interval of 96 ns and the level 1 trigger decision time of 2.2 μs requires a multievent pipeline integrated to the front-end electronics. The design uses 32 switched capacitors on each channel to store the output voltage of the preamplifier. The chip architecture uses the preamplifier to read back any buffer selected by a level 1 trigger before the analog signals are read out serially. Prototypes have been produced in 2 μm CMOS technology. One channel has a width of 44 μm and a length of 2.4 mm. The preamplifier has a single gain stage with active load which offers minimal power dissipation of 280 μW per channel for an open-loop gain of 80. The radiation hardness of the CMOS process was tested in a Co⁶⁰ source, and the chips were found to be functional up to a dose of 150 krad, albeit with increased power (30%) and increased noise slope versus capacitance (100%). Radiation-induced threshold voltage shifts are compensated internally by constant current biasing for the preamplifier