A full custom, high speed, floating point adder

Summary form only. A high-speed pipelined floating point adder for use by the Solenoidal Detector Collaboration (SDC) at the Superconducting Super Collider (SSC) is discussed. The adder uses a unique floating point format. The chip is designed to be a two-stage pipeline and to operate at a peak speed of at least 63 MHz. Static rather than dynamic logic was desired, to permit operation at lower speeds and to ease system testing. The chip is implemented using Orbit Semiconductor´s 1.2 μm n-well process. Simulations indicate that the device will operate at 63 MHz. Initial testing performed at Fermilab, limited by test equipment, indicates speeds of at least 63 MHz, with some tests demonstrating speeds in excess of 150 MHz