A CMOS hybrid random number generator for cryptographic systems

In this paper, a CMOS hybrid random number generator for cryptographic systems is newly proposed. The innovation is that the proposed circuits combine two techniques of pseudo-random number generator and direct amplification in a single chip. Thus, the proposed chip can successfully obtain the strengths of two techniques, and eliminate the weakness of both. The bit rate is 5M bps. The energy requirement for per bit producing is 338 μW/MHz. The chip area is 0.704 × 0.779 mm². The proposed chip is suitable for cryptographic systems.