A pipelined 4 by 12-bits domino logic VLSI adder

A four 12-bit numbers adder fabricated using a 1.2 μm N-well CMOS process is presented. It is proposed for use in the computation of the pipelined energy sums in the detectors at the Superconducting Super Collider (SSC). It comprises three 12-bit adders organized as a two-stage pipeline. To compute the final carry bit, the carry-select technique applied to five 4-bit adders is used. The 4-bit adders use the carry-lookahead method to compute their carriers. In order to reduce the circuit area and to simplify its structure the multiple-output domino logic design style is used. The first stage of the pipeline (two adders) performs two 12-bit additions in parallel while the second stage (one adder) finishes up the previously started computation. The pipeline is driven using a two-phase clocking strategy by processing a single-phase external clock. A worst-case throughput of 18 ns is achieved. A built-in facility for testing the first stage of the pipeline is included. The area of the circuit is 1425×5510 μm²; it has 76 pads; and it was packed in a 132 PGA. The transistor count is 6639. The dissipated power, at 18-ns clock, is ≈0.75 W. The circuit has been fabricated through MOSIS, and a yield of ≈80% for a lot of 50 chips was found