An integrated high performance fastbus slave interface

A high-performance CMOS fastbus slave interface ASIC (application-specific integrated circuit) supporting all addressing and data transfer modes defined in the IEEE 960-1986 standard is presented. The Fastbus Slave Integrated Circuit (FASIC) is an interface between the asynchronous Fastbus and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32-b microprocessor. The FASIC is a programmable device, enabling its direct use in many different applications. A set of programmable address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 Mbytes/s to Fastbus can be obtained using an internal FIFO (first in, first out) in the FASIC to buffer data between the two buses during block transfers. Message passing from Fastbus to a microprocessor on the slave module is supported. A compact (70 mm×170 mm) Fastbus slave piggyback subcard interface including level conversion between ECL (emitter coupled logic) and TTL (transistor transistor logic) signal levels has been implemented using surface mount components and the 208-pin FASIC chip