Data parallel fault simulation

Author

Amin, Minesh B. ; Vinnakota, Bapiraju

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1995

fDate

2-4 Oct 1995

Firstpage

610

Lastpage

615

Abstract

Fault simulation is a compute intensive problem. Data parallel simulation on multiple processors is one method to reduce fault simulation time. We discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. The fault set partitioning technique is simple, can itself be parallelized, and can be implemented with extreme ease. Therefore, the technique can be used on a low cost parallel resource, such as a network of workstations

Keywords

circuit analysis computing; fault diagnosis; logic CAD; logic partitioning; logic testing; parallel programming; compute intensive problem; data parallel fault simulation; fault set partitioning technique; fault simulation time; logic gate level; low cost parallel resource; multiple processors; workstations; Circuit faults; Circuit simulation; Computational modeling; Fault detection; Logic circuits; Logic design; Logic gates; Parallel processing; Partitioning algorithms; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-7165-3

Type

conf

DOI

10.1109/ICCD.1995.528931

Filename

528931