A feasibility study of proximity interconnect technology utilizing transmission line coupling

Presented in this paper is a feasibility study of a chip stacking technology for very high bandwidth communication. This technology utilizes transmission line coupling between coplanar differential lines constructed in metal layers of two chips placed facing each other such that the differential pairs are overlapped with a spacing of many microns. In previous study we demonstrated communication at 12.5 GHz between two differential pairs of transmission lines fabricated on different metal layers in a single chip. As the next step of the study, we developed the second test chip to demonstrate actual communication between two LSI chips using this technology. The test chip includes a high-speed hysteresis-type receiver that extracts the original digital signals from differentiated signals result from the coupling region. In this chip, effect of AC coupling capacitors placed between the driver output and the transmission-line-coupling region in order to reduce power consumption can be also investigated. Evaluation of the second test chip is in progress.