FPGA-accelerator system for computing biologically inspired feature extraction models

Neuromorphic algorithms for computer-based vision may be the next step towards improving the way computers gather and interpret visual information. However, these algorithms typically have high computational demands making them difficult to deploy in embedded environments where power consumption is equally as important as performance. In this paper, we present an embedded implementation of a ventral visual pathway model, HMAX. We describe an embedded FPGA system that implements the model, as well as accelerator engines necessary to ensure adequate performance. The final system is shown to operate within a power budget of 3W while achieving up to 16.5X speedup over a pure embedded processor implementation.