A Register Framework for Network Processors with Banked Register File

Ubiquitous computing disappears from people´s consciousness. To achieve the transparence, tremendous computing power is in need not only in WLAN where users access directly but also in the Internet where information is retrieved and sent. Bandwidth is crucial to improve userpsilas transparent experience when providing services such as video on demand. Network processors (NPs) are specialized design for fast packet processing to achieve a broad bandwidth. The banked register file on NPs is to provide operands parallel fetching and support a large number of registers to reduce memory access, whereas it may also impose some restrictions and problems. This paper discusses the dual-bank register allocation problem for Intelpsilas network processor IXP. Its register file is physically partitioned into two banks. If two source operands are specified in an instruction, they must come from different banks. This makes the IXP register allocator, which allocates registers and assigns bank, tricky and different from conventional ones. We first present an algorithm that provides optimal solution to the graph partition problem. Then a framework for IXP register allocation is established with it. Experimental result shows the framework is effective in practice.