Title :
Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment
Author :
Metzger, M. ; Bastien, F. ; Rousseau, F. ; Vachon, J. ; Aboulhamid, E.M.
Author_Institution :
Montreal Univ., Que.
Abstract :
A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined rules. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach
Keywords :
formal verification; logic CAD; network operating systems; system-on-chip; systems analysis; AMBA bus model; CAD tools; ESys.NET; introspection mechanisms; semi-formal verification; system-level design environment; system-on-chip; Design automation; Electronic design automation and methodology; Genetic programming; Hardware design languages; Java; Reflection; Runtime; Software standards; System-level design; System-on-a-chip;
Conference_Titel :
Rapid System Prototyping, 2006. Seventeenth IEEE International Workshop on
Conference_Location :
Chania, Crete
Print_ISBN :
0-7695-2580-6
DOI :
10.1109/RSP.2006.22
