• DocumentCode
    1930162
  • Title

    Defining a process for rapid processor selection and algorithm development

  • Author

    Dahnoun, N. ; Brand, J.

  • Author_Institution
    Sch. of Electron., Univ. of Bristol, Bristol, UK
  • fYear
    2011
  • fDate
    9-11 May 2011
  • Firstpage
    259
  • Lastpage
    262
  • Abstract
    The digital world is undoubtedly upon us. With so many ground breaking digital technologies in the consumer space, from iPads to 3-D TV´s, it is clear that innovation is the key to success in today´s market. Some might say, more important than innovation is the ability to take an idea from concept to prototype and from prototype to production in a timely manner, ideally less than two years. As Moore´s Law continues to hold true, the window of opportunity to get a product to market is shrinking and engineers need to be smarter about their processor selection. Cost is not always the key to success. Software portability is increasingly important, coupled with familiarity of tools and development environment. With these thoughts in mind, the following paper addresses the engineering need to rapidly prototype key algorithms across a selection of processor architectures (ARM, DSP, System-on-Chip (SoC)), using standard benchmarking techniques in a familiar IDE.
  • Keywords
    digital signal processing chips; system-on-chip; 3D TV; ARM; DSP; IDE; Moore´s Law; benchmarking technique; development environment; digital technology; iPads; processor architecture; rapid processor selection; software portability; system-on-chip; Benchmark testing; Computer architecture; Digital signal processing; Hardware; Instruments; Software; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Systems, Signal Processing and their Applications (WOSSPA), 2011 7th International Workshop on
  • Conference_Location
    Tipaza
  • Print_ISBN
    978-1-4577-0689-9
  • Type

    conf

  • DOI
    10.1109/WOSSPA.2011.5931467
  • Filename
    5931467