On the stability of DSP based P-I phase-locked loops containing matched filter delays

Phase locked loops (PLL) are designed to align the frequency and the phase of the PLL phase accumulator with the frequency and phase of a complex sampled data input sinusoid. When the PLL is required to align the phase slope and phase of the local DDS with the phase slope and phase of a suppressed carrier modulated input signal the PLL phase detector must be augmented by a non-linear process that forms the underlying carrier. A common process estimates the instantaneous envelope of the modulated waveform and removes the modulation to expose the underlying carrier. Reliable estimates of the modulation are formed with the aid of a matched filter and an auxiliary timing recovery process. The matched filter process occurs inside the PLL loop and contributes additional loop delay. Delay inside a feedback loop is undesirable since it tends to destabilize the loop. We examine the effect of this excess loop delay and present intuitive design constraints that assure loop stability.