A chip for self-organizing feature maps

The use of self-organizing feature maps in real-time applications requires a high computational performance. Especially for embedded systems neural network chips are needed. In this paper a fabricated integrated circuit for self-organizing feature maps is presented. The architecture of this digital chip is based on the idea, that restrictions to the algorithm can simplify the implementation. Using the Manhattan Distance and a special treatment of the adaptation factor α decreases the necessary chip area, so that a high number of processor elements can be integrated on one chip. The effects of these restrictions on the function of the self-organizing feature map are discussed. The paper concludes with performance figures for a system architecture based on these chips