Title :
An algorithm for multiplication modulo (2∧N-1)
Author :
Wang, Zhongde ; Jullien, G.A. ; Miller, W.C.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
Abstract :
This paper proposes an efficient algorithm for multiplication modulo (2N-1). To achieve high speed, the Wallace tree is adopted for the multiplier. The Wallace tree multiplier exhibits a more regular structure than binary Wallace tree multipliers, and comparisons with published designs demonstrates advantages of our multiplier architecture in both speed and hardware
Keywords :
multiplying circuits; residue number systems; trees (mathematics); Wallace tree multiplier; algorithm; high speed architecture; multiplication modulo (2∧N-1); Arithmetic; Hardware; Logic; Table lookup; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.593165
