• DocumentCode
    1931332
  • Title

    A parallel architecture for arithmetic coding and its VLSI implementation

  • Author

    Lee, Horng-Yeong ; Lan, Leu-Shing ; Sheu, Ming-hwa ; Wu, Chien-Hsing

  • Author_Institution
    Dept. of Electron. Eng., Nat. Yunlin Inst. of Technol., Taiwan
  • Volume
    3
  • fYear
    1996
  • fDate
    18-21 Aug 1996
  • Firstpage
    1309
  • Abstract
    A new parallel architecture for arithmetic coding is presented in this paper. By dividing the input symbols into a number of groups and processing them in parallel, significant speed-up can be achieved in comparison with existing architectures. The advantages of this parallel architecture are its easier expandability, higher speed, and smaller latency. The parallel arithmetic coder has also been implemented on VLSI using the VHDL technique. The resultant chip layout has a size of 4993×6503 μm2
  • Keywords
    VLSI; arithmetic codes; data compression; hardware description languages; integrated circuit layout; parallel architectures; VHDL technique; VLSI implementation; arithmetic coding; chip layout; data compression; expandability; input symbols; latency; parallel architecture; speed; Arithmetic; Computational complexity; Costs; Data compression; Delay; Encoding; Entropy; Huffman coding; Parallel architectures; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996., IEEE 39th Midwest symposium on
  • Conference_Location
    Ames, IA
  • Print_ISBN
    0-7803-3636-4
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1996.593169
  • Filename
    593169
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1931332