DocumentCode
1932016
Title
Improving Multi-Core System Dependability with Asymmetrically Reliable Cores
Author
Ungsunan, Peter D. ; Lin, Chuang ; Gai, Yi ; Kong, Xiangzhen
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
fYear
2009
fDate
16-19 March 2009
Firstpage
1252
Lastpage
1257
Abstract
An emerging problem facing future high performance multi-core processors is transient faults caused by radiation, noise and other factors. These faults will likely make future multi-core processors less reliable as chip features shrink and the number of cores increase. To address this problem, we propose a new and practical systems approach of managing and allocating reliability according to software process requirements. The asymmetric multi-core architecture is based on cores with differing reliabilities. Critical and non-critical software components are identified and matched with the higher reliability cores. We show that by using asymmetrically reliable cores the overall system failure rate can be reduced by several times when critical processes can be isolated and executed by higher reliability cores, while offering the same or better overall performance, power utilization and chip area as symmetric cores.
Keywords
microprocessor chips; asymmetric multi-core architecture; asymmetrically reliable cores; multi-core processors; multi-core system dependability; software process requirements; symmetric cores; transient faults; Circuit faults; Computer architecture; Fault tolerance; Hardware; Logic; Multicore processing; Power system reliability; Redundancy; Risk management; Semiconductor device noise; Dependability; Multi-core; Reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Complex, Intelligent and Software Intensive Systems, 2009. CISIS '09. International Conference on
Conference_Location
Fukuoka
Print_ISBN
978-1-4244-3569-2
Electronic_ISBN
978-0-7695-3575-3
Type
conf
DOI
10.1109/CISIS.2009.95
Filename
5066957
Link To Document