A Design Scheme of Toggle Operation Based Johnson Counter with Efficient Clock Gating

The performance of any system strongly depends on effective design methods applied on various segments of that system. To provide an intelligent and smart architecture of a computer system, a dedicated design is needed which is both power friendly and less complicated. As computer system consists of sequential circuits mostly, it is very important to design sequential circuits effectively and flawlessly for ensuring least power dissipation and architectural simplicity. Different kinds of counters are considered to be very important segments of sequential circuit system. In this paper, we have proposed a design scheme to develop a Johnson counter with necessary clock gating which is based on toggle operation of J-K flip-flops. This design scheme is more sophisticated and prominent than the conventional shift register based design as this scheme provides fewer interconnections and comparatively lower power dissipation.