Optimisation of a 5 nm ONO-multilayer-dielectric for 64 Mbit DRAMs

The impact of the thicknesses of the nitride- and oxide layers on the performance of a 5nm ONO-layer was investigated. For an optimized 5nm ONO-dielectric tbd 63% at 5MV/cm was found to be above 10¹²sec. In this dielectric the charge transport in the oxide layers is due to direct tunneling processes and the wear-out properties are dominated by the nitride layer. The limiting factors for the reduction of the individual layers of the stacked dielectric are discussed.