ASIC prototyping with reprogrammable implementations of large ASICs

Many users of ASIC technologies are switching to ASIC prototyping on FPGAs for lower cost functional verification which is also a reprogrammable implementation that allows the user to make quick design changes for faster development time. This paper presents a new ASIC prototyping process that provides for large ASIC migration to LUT-based netlists (e.g., XILINX/4000 or ALTERA/FLEX) and routing support for reprogrammable interconnect between FPGAs (e.g., APTIX FPICs or ICUBE FPIDs). Comparisons with MCNC and industrial benchmarks show improvements over XILINX NEOCAD and ALTERA MAXPLUSII mapping and partitioning tools