Title :
Systolic modular VLSI architecture for multi-model neural network implementation
Author :
Moreno, J.M. ; Madrenas, J. ; Cabestany, J.
Author_Institution :
Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
Reviews the basic principles to be considered when mixed analog/digital alternatives for implementing neural models are considered. Starting from a generic systolic architecture, the authors adapt its internal structure in order to permit the modular implementation of a wide range of artificial neural network models. After analyzing the basic computational resources required by the considered neural models, some basic building blocks have been identified and implemented. The authors results show that the proposed approach is suitable for building high throughput physical realizations capable to adapt their resources so as to emulate a wide variety of neural network models
Keywords :
VLSI; mixed analogue-digital integrated circuits; neural chips; systolic arrays; artificial neural network models; generic systolic architecture; mixed analog/digital alternatives; multi-model neural network implementation; systolic modular VLSI architecture; Analog memory; Artificial neural networks; Buildings; Computer architecture; Emulation; Neural network hardware; Neural networks; Neurons; Throughput; Very large scale integration;
Conference_Titel :
Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on
Conference_Location :
Turin
Print_ISBN :
0-8186-6710-9
DOI :
10.1109/ICMNN.1994.593229