Architecture of a 50 MFIPS fuzzy processor and the related 1 μm VLSI CMOS digital circuits

Author

Gandolfi, Enzo ; Masetti, Massimo ; D´Antone, I. ; Gabrielli, Alessandro ; Spotti, Marco

Author_Institution

Dipartimento di Fisica, Bologna Univ., Italy

fYear

1994

fDate

26-28 Sep 1994

Firstpage

125

Lastpage

133

Abstract

This paper deals with two problems: the first concerns the design of the HW architecture of a high speed fuzzy processor that can work at 50 Mega fuzzy inference per second (MFIPS). It has eight 7 bit inputs and one 7 bit output. It is foreseen to apply it to a trigger device in HEP (High Energy Physics) experiments, the second one concerns the 1 μm CMOS VLSI design of the fuzzification and inference process, the MIN-MAX and the defuzzifier circuits, using the ES2 standard cells, which work with a delay less than 20 ns. These circuits have already been realized and tested. The design has been done using Cadence tools we got from Eurochip. At present a 4 input fuzzy processor has been fully designed and it has been recently sent to ES2 to be realized. Fuzzy processors that run at this speed are not available on the market and this is the innovative feature of this design

Keywords

CMOS logic circuits; VLSI; fuzzy logic; inference mechanisms; 1 μm VLSI CMOS digital circuits; 1 micron; 50 MFIPS fuzzy processor; Cadence tools; ES2 standard cells; Eurochip; High Energy Physics; CMOS digital integrated circuits; CMOS process; Delay; Digital circuits; Electronic mail; Event detection; Neural networks; Particle tracking; Physics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on

Conference_Location

Turin

Print_ISBN

0-8186-6710-9

Type

conf

DOI

10.1109/ICMNN.1994.593234

Filename

593234