DocumentCode
1932877
Title
Application of timing variation modeling to speedpath diagnosis
Author
Dehbashi, Mehdi ; Fey, Görschwin
Author_Institution
Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
fYear
2012
fDate
19-20 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
The impact of timing variations on the performance of Very-Large-Scale Integrated (VLSI) circuits is increasing as the feature sizes shrink down into the nanometer scale. Timing variations induced by process, environmental or other effects may lead to a failing speedpath. In this paper, first a functional model of circuit timing is constituted. Then, timing variations are added to the model. Afterwards, this model is utilized to diagnose failing speedpaths.
Keywords
VLSI; integrated circuit modelling; integrated circuit reliability; VLSI circuits; circuit timing functional model; speed path diagnosis; timing variation modeling; very-large-scale integrated circuit; Circuit faults; Clocks; Integrated circuit modeling; Logic gates; Solid modeling; Timing; Vectors; diagnosis; speedpath; timing variation;
fLanguage
English
Publisher
ieee
Conference_Titel
System, Software, SoC and Silicon Debug Conference (S4D), 2012
Conference_Location
Vienna
ISSN
2114-3684
Print_ISBN
978-1-4673-2454-0
Electronic_ISBN
2114-3684
Type
conf
Filename
6338150
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