Title :
Optimal well design for triple-well CMOS digital circuits with back-biasing V/sub T/ control
Author :
Ionita, Razvan ; Vladimirescu, Andrei
Author_Institution :
Inst. Superieur d´´Electronique de Paris, France
Abstract :
A model of the substrate well in circuits implemented in a triple-well deep-submicron technology is presented. This model takes into account the distributed nature of the well and the distance of the bulk of each transistor from the well contacts. The model is applied to CMOS standard-cell circuits with back-biasing VT control to study the impact of the number of gates placed in the same well and the well contacts´ placement, and the resistance between the well contacts and the bulk of the transistors. The lumped equivalent network of the well is derived as a function of the number of gates in the well and the results of simulations of the circuit-in-the-well lead to guidelines for optimal well sizing and contact placement. The performance and power consumption of logic circuits is analyzed leading to conclusions for optimal design and layout.
Keywords :
CMOS digital integrated circuits; circuit simulation; contact resistance; equivalent circuits; semiconductor device models; back biasing control; lumped equivalent network; optimal well design; triple well CMOS digital circuits; well contacts; CMOS digital integrated circuits; CMOS technology; Circuit simulation; Contact resistance; Digital circuits; Energy consumption; Guidelines; Logic circuits; Optimal control; Semiconductor device modeling;
Conference_Titel :
Electron Devices, 2005 Spanish Conference on
Conference_Location :
Tarragona
Print_ISBN :
0-7803-8810-0
DOI :
10.1109/SCED.2005.1504412