A hardware implementation of a binary neural associative memory

Author

Kennedy, J.V. ; Austin, J.

Author_Institution

Dept. of Comput. Sci., York Univ., UK

fYear

1994

fDate

26-28 Sep 1994

Firstpage

178

Lastpage

185

Abstract

A significant bottleneck to the use of associative memories in real-time systems is the amount of data that requires processing. The aim of this paper is to present the work that produced a dedicated hardware design that will run a major part of the ADAM algorithm. The work selected a portion of the algorithm to implement using FPGA technology. The Sum And Threshold (SAT) processor has been simulated and shown to process data fifty times faster than the current DSP based system that uses a dedicated peripheral processor. The paper includes analysis of the speed characteristics of the SAT processor, along with an analysis of the design. The design analysis highlights a bottleneck in the design to which a solution is proposed for future work

Keywords

content-addressable storage; field programmable gate arrays; image processing; neural nets; real-time systems; ADAM algorithm; Advanced Distributed Associative Memory; binary neural associative memory; dedicated hardware design; design analysis; hardware implementation; real-time systems; scene analysis; sum/threshold processor; Algorithm design and analysis; Associative memory; Computer science; Decoding; Digital signal processing; Hardware; Image analysis; Image processing; Image storage; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on

Conference_Location

Turin

Print_ISBN

0-8186-6710-9

Type

conf

DOI

10.1109/ICMNN.1994.593263

Filename

593263