Signal and timing analysis of a phase-domain all-digital phase-locked loop with reference retiming mechanism

In extension to our previous work, where we have introduced a uniform z-domain model, we elaborate system level properties, signal characteristics, and the time-varying nature of phase-domain all-digital phase-locked loops (ADPLLs). The uniform z-domain model neglects that the ADPLL architecture requires a non-uniform reference clock for the entire digital logic. The so called retimed reference clock synchronizes the fast digitally controlled oscillator (DCO) output clock with the slow reference clock. We first review the uniform z-domain model and the ADPLL architecture with a reference retiming mechanism. In analogy to the uniform z-domain model we introduce a non-uniform z-domain model to investigate the time-varying properties of the system. The non-uniform retimed reference clock, its periodic pattern in lock, and the resulting phase signals with time-varying slopes are analyzed with respect to the synthesized frequency.