Analysis of static and dynamic behaviour of SiC and Si devices connected in cascode configuration

Author

Mihaila, A. ; Udrea, F. ; Azar, R. ; Brezeanu, G.

Author_Institution

Dept. of Eng., Cambridge Univ., UK

Volume

2

fYear

2001

fDate

37165

Firstpage

333

Abstract

This paper presents an analysis of the static and dynamic behaviour of a 1.2 kV SiC vertical JFET. The JFET can block voltages up to 1450 V (for V_GS=80 V), with a specific on-resistance as low as 2.3 mΩcm². The mixed-mode performance is investigated by coupling the SiC JFET in a cascode circuit with a low power Si MOSFET. Comparing the circuit performance to that of a SiC trench MOSFET, it turns out that the SiC/Si cascode is almost twice faster than the MOSFET. Coupling this with the fact that the SiC/Si cascode pair has better on-state performance, it is concluded that the cascode is a superior alternative to the classical SiC trench MOSFET

Keywords

MOSFET; junction gate field effect transistors; power field effect transistors; power semiconductor switches; semiconductor device models; silicon compounds; wide band gap semiconductors; 1.2 kV; 1450 V; SiC vertical JFET/low power Si MOSFET; SiC-Si; blocking voltages; cascode configuration; circuit performance; dynamic behaviour; mixed-mode performance; numerical investigation; on-state performance; power switching applications; specific on-resistance; static behaviour; Avalanche breakdown; Circuit optimization; Coupling circuits; Dielectric materials; Dielectrics and electrical insulation; JFET circuits; MOSFET circuits; Power MOSFET; Silicon carbide; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2001. CAS 2001 Proceedings. International

Conference_Location

Sinaia

Print_ISBN

0-7803-6666-2

Type

conf

DOI

10.1109/SMICND.2001.967477

Filename

967477