Logi-thermal simulation of digital CMOS ICs with emphasis on dynamic power dissipation

Due to technology scaling and increasing power density thermal issues in today´s VLSI integrated circuits are of very high importance. Nowadays, more than a half of IC failures is caused by exceeded heating of a semiconductor structure. Therefore, it is necessary to constantly develop accurate methods capable of predicting temperature profile inside the chip structure. We propose a model to obtain variation of temperature in digital CMOS ICs, resulting from dynamic power dissipation. A gate-level logic simulator prepared by authors is coupled with temperature calculation method based on analytical solution of the heat equation. Planar heat sources are represented by a finite area and images method is used to apply proper boundary conditions. Temperature and its influence on propagation delay is calculated in consecutive steps of a simulation. Use of logic simulation instead of circuit-level simulation enables us to save computation time. Moreover, the analytical solution does not have drawbacks specific for numerical methods, e.g. it is not needed to use a mesh. The proposed method let us also observe fast changing temperature variations and propagation delay fluctuations within a small range of time. Ring oscillator circuits were used to show proper operation of implemented software application. Simulations were made for a generic 90 nm technology using basic digital circuits.