DocumentCode
1934192
Title
A high speed self-biased CMOS amplifier IP core
Author
Zhu, Zhangming ; Liu, Lianxi ; Yang, Yintang
Author_Institution
Microelectron. Inst., Xidian Univ., Xi´´an, China
fYear
2005
fDate
28-30 May 2005
Firstpage
6
Lastpage
9
Abstract
A novel high speed 0.25 μm CMOS amplifier IP core is presented which use the complementary self-biasing differential amplifier technique. The proposed amplifier features a 418 MHz unity gain frequency and 375 V/μs slew rate with capacitive load 2pF. The output voltage of the proposed amplifier swings from Vgnd to Vdd and the static power less than 0.32 μW. A Verilog-A behavioral model is presented for the amplifier IP core which contains the important non-idealities of the amplifier.
Keywords
CMOS integrated circuits; differential amplifiers; electronic engineering computing; hardware description languages; 0.25 mum; 375 V; 418 MHz; CMOS amplifier IP core; Verilog-A behavioral model; capacitive load; self-biasing differential amplifier technique; static power; CMOS technology; Differential amplifiers; Equivalent circuits; Frequency; Hardware design languages; Microelectronics; Power amplifiers; Power dissipation; Semiconductor device modeling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN
0-7803-9005-9
Type
conf
DOI
10.1109/IWVDVT.2005.1504450
Filename
1504450
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