Title :
High-speed monolithic CMOS limiting amplifier with low-pass network
Author :
Fuhua, Li ; Qiuping, Huang ; Min, Qian
Author_Institution :
Dept. of Microelectron., Suzhou Univ., China
Abstract :
To achieve wide-bandwidth performance, this paper proposes an on-chip high-speed limiting amplifier that employs a low-pass network topology. To avoid the parasitic effects of the on-chip spiral inductor, several short circuit coplanar stripline stubs fabricated with thicker top metal layer are used as passive inductors. The gain and bandwidth of the amplifier is studied employing a simplified MOSFET model, and simulated results are given for two different circuits structure. Finally, a test amplifier with a bandwidth of 6 GHz, gain of 15 dB and power dissipation of 70 mW is fabricated with the standard 1.8-V 0.18-μm digital CMOS process.
Keywords :
CMOS digital integrated circuits; MOSFET; amplifiers; integrated circuit testing; mixed analogue-digital integrated circuits; network topology; 0.18 mum; 1.8 V; 15 dB; 6 GHz; 70 mW; MOSFET model; digital CMOS process; high-speed monolithic CMOS limiting amplifier; low-pass network topology; on-chip high-speed limiting amplifier; on-chip spiral inductor; passive inductors; short circuit coplanar stripline stubs fabrication; wide-bandwidth performance; Bandwidth; Broadband amplifiers; Circuit simulation; Inductors; MOSFET circuits; Network topology; Network-on-a-chip; Semiconductor device modeling; Spirals; Stripline;
Conference_Titel :
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN :
0-7803-9005-9
DOI :
10.1109/IWVDVT.2005.1504452
