• DocumentCode
    1934421
  • Title

    A new 0·5μm2 DRAM cell with internal charge gain investigated by 2D transient device simulation

  • Author

    Richter, R. ; Ehwald, K.E. ; Heinemann, B. ; Matzke, W.-E. ; Gajewski, H ; Winkler, W.

  • Author_Institution
    Institute for Physics of Semiconductors, Academy of Sciences of the GDR, Walter-Korsing-Str. 2, 1200 Frankfurt (Oder), GDR
  • fYear
    1990
  • fDate
    10-13 Sept. 1990
  • Firstpage
    173
  • Lastpage
    176
  • Abstract
    The Vertically Integrated Gain (VIG) cell is a new DRAM structure for 64/256 Mbit ORAMs. By using a trench structure and 0.25 μm design rules a cell size of 0.55μm2 is attainable. The cell function bases on merging 2 bipolar junction transistors (BJT), 1 junction field effect transistor (JFET) and 2 capacitors. 20 transient device simulation is used to investigate the electrical behaviour of the VIG cell. A high read out signal, 2 control lines, operation voltages between 0 and 5 volts only and the capability to maintain the stored information during read operation are the main features of the proposed DRAM cell.
  • Keywords
    Capacitors; Circuits; FETs; Mathematics; Merging; Physics; Publishing; Random access memory; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1990. ESSDERC '90. 20th European
  • Conference_Location
    Nottingham, England
  • Print_ISBN
    0750300655
  • Type

    conf

  • Filename
    5436440
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1934421