Title :
RISC Processing In Fastbus
Author :
Atiya, M. ; Haggerty, J. ; Ng, C. ; Sambamurti, A. ; Strzelinski, R.
Author_Institution :
Brookhaven National Laboratory
Keywords :
Coprocessors; Data acquisition; Data analysis; Fastbus; Hardware; Logic; Random access memory; Read-write memory; Reduced instruction set computing; Testing;
Conference_Titel :
Nuclear Science Symposium, 1990. Conference record : Including Sessions on Nuclear Power Systems and Medical Imaging Conference, 1990 IEEE
Print_ISBN :
0-87942-683-7
DOI :
10.1109/NSSMIC.1990.693340
