Title :
Design of PLL system based Verilog-AMS behavior models
Author :
Lian-xi, Liu ; Yin-tang, Rang ; Zhang-ming, Zhu ; Yani, Li
Author_Institution :
Key Lab of Minist. of Educ. for Wide Band-Gap Semicond. Mater. & Device, Xidian Univ., Xi´´an, China
Abstract :
A top-down design method on analog PLL system based Verilog-AMS HDL behavior models is proposed. A PLL contained a VCO behavior model with center frequency 120 MHz and a two-order passive filter with cut-off frequency 300.0 KHz is implemented. The Verilog-AMS behavior models are verified and used in PLL system simulation by the tools of Cadence spectre.
Keywords :
hardware description languages; passive filters; phase locked oscillators; 120 MHz; 300 kHz; Cadence spectre tools; Verilog-AMS HDL behavior models; analog PLL system design; top-down design method; two-order passive filter; voltage controlled oscillators; Application specific integrated circuits; Circuit simulation; Costs; Cutoff frequency; Design methodology; Hardware design languages; Libraries; Mathematical model; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN :
0-7803-9005-9
DOI :
10.1109/IWVDVT.2005.1504466
