A programmer´s view of the 80960 architecture

Author

McGeady, S.

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

1989

fDate

Feb. 27 1989-March 3 1989

Firstpage

4

Lastpage

9

Abstract

The 80960 processor integrates many architectural features normally found in RISC (reduced-instruction-set computer) processors with others found in more traditional architectures. The result is a processor providing high performance while presenting few difficulties for either applications or compiler writers. A discussion is presented of the programming model of the 960, including aspects of the instruction set and the register architecture. Techniques for effective use of the 960 from both assembly language and high-level languages are discussed, including the subroutine calling sequence designed for the architecture.<>

Keywords

instruction sets; microprocessor chips; programming; Intel 80960 microprocessor; assembly language; high-level languages; instruction set; programming model; register architecture; subroutine calling sequence; Algorithms; Application software; Assembly systems; Computer architecture; High level languages; Kernel; Operating systems; Optimizing compilers; Program processors; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-1909-0

Type

conf

DOI

10.1109/CMPCON.1989.301894

Filename

301894