Title :
80960-next generation
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fDate :
Feb. 27 1989-March 3 1989
Abstract :
A discussion is presented of the next generation core for the 80960 family of embedded processor chips. It is shown that the next generation 960 core incorporates several features for high performance. It has wide and concurrent internal buses. It can decode and issue a sustained two instructions per clock even with loads and branches. It implements branch lookahead with branch prediction to minimize pipeline breaks. It manages the parallelism and multiple functional units by using resource scoreboarding techniques. It is a modular, high-performance core designed for the embedded processor market. The goals of the core design, the basic microarchitecture, the pipeline, and the key performance features are examined.<>
Keywords :
computer architecture; microprocessor chips; Intel 80960 microprocessors; branch lookahead; branch prediction; embedded processor chips; microarchitecture; multiple functional units; next generation core; parallelism; performance features; resource scoreboarding; Clocks; Computer architecture; Decoding; Logic arrays; Microarchitecture; Microprocessors; Pipelines; Radio frequency; Read only memory; Registers;
Conference_Titel :
COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-1909-0
DOI :
10.1109/CMPCON.1989.301896
