DocumentCode
1934900
Title
Analysis of the subthreshold shift induced by the shallow trench isolation corner in advanced DRAM and flash memories
Author
Tazlauanu, Mihai ; Scansen, Don ; Gibb, Kevin
Author_Institution
Semicond. Insights Inc., Ottawa, Ont., Canada
Volume
2
fYear
2001
fDate
37165
Firstpage
499
Abstract
We have analyzed the effect of shallow trench isolation on transistor performance in state-of-the-art memory circuits. Gate wraparound, corner rounding, and gate oxide thinning are all significant factors that affect the electrical performance. We have identified gate wraparound as the main contributor to the subthreshold shift of the NMOS transistors
Keywords
CMOS memory circuits; DRAM chips; flash memories; isolation technology; CMOS integrated circuit; DRAM; NMOS transistor; corner rounding; electrical characteristics; flash memory; gate oxide thinning; gate wraparound; shallow trench isolation; subthreshold shift; Circuits; Geometry; Leakage current; MOSFETs; Performance analysis; Protection; Random access memory; Scanning electron microscopy; Transmission electron microscopy; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference, 2001. CAS 2001 Proceedings. International
Conference_Location
Sinaia
Print_ISBN
0-7803-6666-2
Type
conf
DOI
10.1109/SMICND.2001.967514
Filename
967514
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