Electrical Characterization of a Submicron Titanium Silicide Local Interconnect Technology

In advanced CMOS technologies the use of a local interconnect technology, under the intermediate oxide provides a means of increasing circuit packing density at the cost of only one additional mask layer. A scheme involving the creation of titanium silicide interconnect has been incorporated in a submicron CMOS technology used for the production of 1 Mbit static RAMs. This paper describes the full electrical characterisation of this local interconnect technology as it is used in this process. It is shown that the titanium/amorphous silicon thickness ratio must be less than 0.38 if silicon suckout from the active area regions is to be avoided. Suckout of silicon may result in increased junction leakage dependent on the silicide strap layout. An increase in the p-channel transistor series resistance may also occur.