Optimization of Submicron n-channel Devices for Performance and Reliability

The DC performance of silicided N-channel devices is characterised primarily by the current drive capability. However, this is adversely influenced by the series resistance of the device which arises primarily from the lightly doped region located between the channel and the highly doped source/drain regions. This region is introduced to meet the lifetime specification of the device by reducing the hot carrier effects at the drain edge. The goal of this investigation was to achieve maximum current drive capability while satisfying the lifetime specifications. Initially N-channel devices with different drain structures were fabricated and their current drive capablities, electric field distributions and lifetimes were characterised. Simulations with MINIMOS-4 were performed and the results were correlated with the measured data. Based on these verified simulations, improved N channel drain structures were then defined and devices with these drain structures were fabricated. These devices proved to have both higher current drive and improved lifetime. However, as expected, adverse short channel effects were seen on these structures. However, a compromise can be achieved that gives better performance and improved lifetime while minimising short channel effects.