Title :
The fully-serial pipelined multiplier
Author :
Shafer, Andrew G. ; Parker, Lyndsi R. ; Swartzlander, Earl E., Jr.
Author_Institution :
Adv. Micro Devices, Austin, TX, USA
Abstract :
This paper presents a new multiplier design which is fully-serial and requires only 1.5N cycles to return a product. This design has been implemented for both unsigned and two´s complement number systems. This design can be pipelined so that each additional multiplication only requires N cycles.
Keywords :
logic design; multiplying circuits; pipeline arithmetic; complement number system; fully-serial pipelined multiplier; multiplier design; Parallel Counter; fully-serial multiplication; sign-magnitude multiplication; two´s complement multiplication;
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4673-0321-7
DOI :
10.1109/ACSSC.2011.6190336
