Compatibility of candidate high permittivity gate oxides with front and backend processing conditions

The need for new, high permittivity dielectrics for gate stacks in CMOS devices is now well recognized. The timescales for the requirements is laid out in recent issues of the Semiconductor Industry Association Roadmap. The most pressing requirement is for low powered MOSFETs. Research into high permittivity candidate dielectrics has therefore proceeded with urgency over the past 3 years. In general, two approaches are possible. Industry would prefer the direct replacement of SiO/sub 2/ as the gate dielectric, while making relatively few changes to the subsequent process conditions. This would require that the alternative dielectric be capable of surviving the high temperature rapid thermal anneals (typically over 1000/spl deg/C) required for dopant activation, in addition to the reducing backend anneals used to ensure low contact resistances for the interconnect structures. An alternative approach is to determine optimum process conditions for the gate dielectric, and adapt the CMOS process flow to accommodate this process. Relatively few resources have to date been expended to determine whether direct replacement is a possibility. This question is thus the research topic addressed in this paper. We address the question by establishing the conditions for thermodynamic stability of candidate dielectrics at elevated temperature, and the conditions under which specific reactions occur. We confirmed our reaction models by measuring the properties of appropriate MOS capacitors after high temperature processing.