Parallel 4×4 transform on bit serial shared memory architecture for H.264/AVC

Many video applications require dedicated hardware to achieve acceptable levels of performance. H.264/AVC, the latest standard for video signal coding, utilizes a 4 times 4 integer transform to concentrate energy of residual data in a few coefficients. This paper presents an implementation and simulation of parallel 4 times 4 transform on bit serial shared memory architecture for H.264/AVC. Compared with the existing parallel implementations, the proposed architecture reduces interconnection resources of physical elements of FPGA device. The results of simulation show that the transform can be realized in real time on bit serial arithmetic.