DocumentCode :
1935684
Title :
Implementation of kernels on the Maestro processor
Author :
Jinwoo Suh ; Kang, D.I.D. ; Crago, Stephen P.
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Arlington, VA, USA
fYear :
2013
fDate :
2-9 March 2013
Firstpage :
1
Lastpage :
6
Abstract :
Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera´s TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.
Keywords :
FIR filters; aerospace computing; fast Fourier transforms; floating point arithmetic; matrix multiplication; microprocessor chips; space vehicles; FFT; FIR filter; FPU; GFLOPS; Maestro processor; Tilera TILE64 processor; floating point unit; kernels implementation; matrix multiplication; microprocessors; multiple cores; power usage; radiation-hardened processor; space applications; vector add; Clocks; Finite impulse response filters; Microprocessors; Multicore processing; Pipelines; Space vehicles; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Aerospace Conference, 2013 IEEE
Conference_Location :
Big Sky, MT
ISSN :
1095-323X
Print_ISBN :
978-1-4673-1812-9
Type :
conf
DOI :
10.1109/AERO.2013.6496949
Filename :
6496949
Link To Document :
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