DocumentCode
1935917
Title
Synthesis of High-Level Decision Diagrams for functional test pattern generation
Author
Ubar, Raimund ; Raik, Jaan ; Karputkin, Anton ; Tombak, Mati
Author_Institution
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
fYear
2009
fDate
25-27 June 2009
Firstpage
519
Lastpage
524
Abstract
In this paper we present two methods for synthesis of high-level decision diagrams (HLDD) for representing digital systems at higher behavior, functional or register-transfer levels. The first method is based on symbolic execution of procedural descriptions, which corresponds to functional representation of systems on the behavioral level. The second one is based on iterative superposition of HLDDs, and the created model corresponds to the high-level structural representation of the system. The second method can be regarded as the generalization of the superposition of BDDs as the basis for generation of structurally synthesized BDDs (SSBDD). Experimental data show the advantages of HLDDs.
Keywords
automatic test pattern generation; binary decision diagrams; network synthesis; shift registers; binary decision diagram; functional test pattern generation; gate-level automatic test pattern generators; high-level decision diagrams; iterative superposition; register-transfer levels; structurally synthesized BDDs; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Data structures; Digital systems; Logic circuits; Logic testing; System testing; Test pattern generators; digital systems; register transfer level modeling decision diagams; superposition of graphs; symbolic execution;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference
Conference_Location
Lodz
Print_ISBN
978-1-4244-4798-5
Electronic_ISBN
978-83-928756-1-1
Type
conf
Filename
5289595
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